1. Field of the Invention
The present invention relates to a method and apparatus for generating a clock signal, and more particularly, to a method and apparatus for generating a clock signal from a reference clock signal.
2. Description of the Related Art
In general, clock signal generators are used in the field of electronic devices, including semiconductors. More particularly, clock signal generators may be used in designing an electronic circuit, which requires a clock signal having a particular frequency to process data. If necessary, the clock signal generator executes frequency division of reference clock signal to generate clock signals having a variety of different frequencies.
Korean Laid-open Patent No. 2000-0065911 discloses preventing glitches produced while generating clock signals, regardless of delay elements, and Japanese Laid-open Patent No. 2001-209454 discloses generating clock signals, which are not integral numbers, using a circuit that generates a polyphase clock.
According to the conventional art, a reference clock signal may be divided by an integer to generate clock signals having a target frequency. For example, a reference clock signal having a frequency of 100 MHz may be divided by integers to generate clock signals having frequencies of 50 MHz, 25 MHz, 12.5 MHz, and so on. However, when a clock signal having a target frequency of 75 MHz is required, a new reference clock signal is necessary. For example, a new reference clock signal having a frequency of 300 MHz, which is the least common multiple of 100 MHz and 75 MHz, is required.
Accordingly, the conventional technology which divides a reference clock signal by an integer to generate clock signals produces limited frequencies of clock signals, and therefore, in practice, a variety of reference clock sources are needed.
It may be possible to generate clock signals having a variety of different frequencies using a phase locked loop (PLL) circuit, but when a PLL circuit is used, a phase locking time can result in operational delays.
Moreover, clock signals having different frequencies generated from a source clock signal are not synchronized with one another. Thus, an additional synchronizer is required for processing data, which decreases processing speed.